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56 SA-1110 Developer’s Manual
Coprocessors
6.2 Coprocessor 15 Definition
The SA-1110 coprocessor 15 contains registers that control the cache, MMU, and write buffer
operation as well as some clocking functions. These registers are accessed using CPRT instructions
to coprocessor 15 with the processor in any privileged mode. Only some of registers 0–15 are
valid; the result of an access to an invalid register is unpredictable. Table 6-1 lists the coprocessor
15 control registers.
6.2.1 Register 0 – ID
Register 0 is a read-only register that returns an architecture and implementation-defined
identification for the device.
Table 6-1. Cache and MMU Control Registers (Coprocessor 15)
Register Register Reads Register Writes
0ID
RESERVED
1
Control Control
2
Translation table base Translation table base
3
Domain access control Domain access control
4
RESERVED RESERVED
5
Fault status Fault status
6
Fault address Fault address
7
RESERVED Cache operations
8
RESERVED TLB operations
9
RESERVED Read buffer operations
10..12 RESERVED RESERVED
13 Read process ID (PID) Write process ID (PID)
14 Read breakpoint Write breakpoint
15 RESERVED Test, clock, and idle
Register 0 – ID Read-Only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
69 Architecture Version Part Number
Stepping
ARM Architecture
Version
01 = Version 4
Part Number B11 = SA1110
Stepping Revision of
SA-1110
0000 = A0 stepping 0100 = B0 stepping 0101 = B1 stepping
0110 = B2 stepping 1000 = B4 stepping 1001 = B5 stepping