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SA-1110 Developer’s Manual 43
ARM Implementation Options
3.2.6 Interrupt Latencies and Enable Timing
The ability to recognize an IRQ or FIQ interrupt is, in part, determined by the I and F bits of the
CPSR. To ensure that a pending interrupt is taken, an interrupt-enabling write to CPSR (msr
instruction) must be separated from an interrupt-disabling write to the CPSR by at least two
instructions.
3.3 Coprocessors
The SA-1110 has no external coprocessor bus, so it is not possible to add external coprocessors to
this device.
The SA-1110 uses the internal coprocessor designated 15 for control of the on-chip MMU, caches,
clocks, and breakpoints. Coprocessor 15 is also used for read-buffer fills and flushes. If a
coprocessor other than 15 is used, then the SA-1110 will take the undefined instruction trap. The
coprocessor load, store, and data operation instructions also take the undefined instruction trap.
Permissions are set so that access to coprocessor 15 is privileged except where protection is
programmable with respect to the read buffer operations.
Note: The write buffer must be flushed prior to loading the read buffer to maintain coherency between the
two buffers. But, if user-mode MCR access is enabled for the read buffer and the flush is attempted
while in user mode, an undefined instruction exception will occur. In this case, the exception
handler must perform the write buffer flush, then return to user mode to execute the read buffer
load. Alternatively, an SWI instruction can be used as a service call to flush the write buffer.