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SA-1110 Developer’s Manual 155
Memory and PC-Card Control Module
10.5.5 SDRAM State Machine
Figure 10-5 shows all possible SDRAM controller states and transitions. Many of the states are
named after the SDRAM commands with which they are coincident and have a fixed duration of
one cycle. Transitions from the other states are determined by the overall memory controller state
and a few SDRAM power-down/self-refresh status/control bits. Most of the states and transitions
may involve multiple SDRAM devices and their internal banks. Only those states shown below
"idle" involve a single bank within a single SDRAM row. If none of the labeled transitions have
their conditions satisfied and no default transition is indicated, the current state is maintained for at
least one more cycle.
A hardware or sleep reset causes the SDRAM state machine to enter the "self-refresh and
clock-stop" state. Then, it is software’s responsibility to complete the appropriate reset procedure
(see Section 10.2.1). The “Clear_E1PIN” and “Clear_KnRUN” transitions (indicated by dotted
lines in Figure 10-5 and achieved by clearing the E1PIN, K1RUN, and/or K2RUN bits of
MDREFR) are provided to allow ultimate software control of the SDRAM memory system’s
low-power modes. They should be used with extreme caution because the resulting states prohibit
automatic transitions for mode register set, read, write, and refresh commands. The
“Auto_Power_Down” and “Auto_Power_Up” transitions (made possible by setting the EAPD
and/or KAPD bits of MDREFR) provide a completely automatic alternative for minimizing power
consumption in the SDRAM memory system.
The following prioritization is used for transitions out of the idle state. If enabled via the EAPD and
KAPD bits, the "Auto_Power_Down" transition occurs when none of the higher priority transitions
are asserted. The "Auto_Power_Up" transition occurs when "Enter_Sleep", "Refresh",
"New_Enable", or "New_Access" is asserted during the "power-down" state.
High priority - "Enter_Sleep"
"Set_SLFRSH"
"Clear_E1PIN"
"Refresh"
"New_Enable"
"New_Access"
Low priority - "Auto_Power_Down"
When the internal system bus causes a new access, the state machine executes an ACT command.
Then the SA-1110 executes one read or write command for each beat of a burst access. The last (or
single) beat uses the autoprecharge command (READAP or WRITEAP), but all preceding beats
use the nonprecharge command (READ or WRIT). Figure 10-6, Figure 10-7,andFigure 10-8
show timing diagrams of SDRAM transactions.