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SA-1110 Developer’s Manual 175
Memory and PC-Card Control Module
If the SMROM_EN pin is held high, MDCAS00, SMCNFG:CL0, and SMCNFG:RL0 must
maintain their hardware or sleep reset values to avoid mismatches in RAS latency between the
SA-1110 and boot SMROM following a subsequent hardware or sleep reset.
The following prioritization is used for transitions from the "Idle" state. Some of these variables
merely stall the SMROM state machine while performing DRAM/SDRAM tasks. If enabled via
the MDREFR:EAPD and MDREFR:KAPD bits, the "Auto_Power_Down" transition occurs when
none of the higher priority transitions are asserted. The "Auto_Power_Up" transition occurs when
"New_Enable" or "New_Access" is asserted during the "Power-down" state.
High priority - "Enter_Sleep"
"New_Enable"
"New_Access"
Low priority - "Auto_Power_Down"
When the internal system bus causes a new access, the state machine will execute an ACT
command. Then the SA-1110 executes one READ command for each single or burst access. For
burst-of-N transfers, (N-1) NOP commands follow the READ. Finally, a STOP command
terminates all transfers smaller than burst-of-eight. Figure 10-18 shows a timing diagram of an
SMROM transaction.