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SA-1110 Developer’s Manual 289
Peripheral Control Module
11.8.9.1 Transmit FIFO Service (TFS)
The TFS bit will be automatically set to 1 if there are 8 or less bytes remaining in the Transmit Data
FIFO. TFS = 1 is used to request DMA service to fill the FIFO.
11.8.9.2 Transmit Packet Complete (TPC)
The TPC bit will be automatically set to 1 when the SA-1110 UDC has sent an entire packet to the
Host. When the TPC bit is set, the TIR bit in the UDC Status/Interrupt Register will be
automatically set to 1 if transmit interrupts are enabled. The TPC bit can be used to validate the
other status/error bits in UDCCS2. The TPC bit is cleared to 0 by the CPU writing a 1 to it. While
the TPC bit is set, the SA-1110 UDC will issue NAK Handshakes to all IN Tokens.
11.8.9.3 Transmit Packet Error (TPE)
The TPE bit is automatically set to 1 to indicate that the Host did not issue an ACK Handshake to
the current packet. The TPE bit is valid only when the TPC bit is set. The TPE bit is automatically
cleared to 0 when the TPC bit is cleared.
0h 8000 0018 UDCCS2 Read/Write
7 6 5 4 3 2 1 0
Reserved FST SST TUR TPE TPC
TFS
Reset
0 0 0 0 0 0 0 ?
Bits Name Description
0 TFS
Transmit FIFO service (read-only).
0 – Transmit FIFO has more than 8 bytes.
1 – Transmit FIFO has 8 bytes or less.
1TPC
Transmit packet complete (read/write 1 to clear).
0 – Error/status bits invalid.
1 – Transmit packet has been sent and error/status bits are valid.
2TPE
Transmit packet error (read-only).
0 – Transmit packet was received with no errors.
1 – Transmit packet has errors and the Host did not issue ACK. Valid only when RPC is set.
3TUR
Transmit FIFO underrun.
1 – Transmit FIFO experienced an underrun. Valid only when TPC is set.
4SST
Sent STALL (read/write 1 to clear).
1 – STALL handshake was sent. Valid only when TPC is set.
5FST
Force STALL (read/write).
1 – Issue STALL handshakes to IN tokens.
7..6 —
Reserved.
Always read zero.