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SA-1110 Developer’s Manual 157
Memory and PC-Card Control Module
Figure 10-6. SDRAM 1-Beat Read/Write/Read Timing for 4 Bank x 4 M x 4 Bit Organization
(64 Mbit)
A6636-02
CPU Clock
Memory
Clock
SDCLK
SDCKE
command
DRA13-12
DRA11
DRA10
DRA9-0
nSDRAS
nRAS/nSDCS
nSDCAS
RD/nWR
D0 D0
ACT READAP ACT WRITEAP ACT READAP
nWE
D0
nCAS/DQM
Contents of DRAM register fields:
MDCNFG:DTIM0=1 MDCNFG:DWID0=0 MDCAS00=0101 0101 0101 0101 0101 0101 0101 0111(binary)
MDCNFG:DRAC0=5 MDCNFG:CDB20=0 MDCNFG:TRP0=1 MDCNGF:TDL0=2 MDCNFG:TWR0=3
D
firstlast
time
Bank Bank Bank
Row Row Row
12345678910111213141516171819202122
T
rcd
TDL TRP+1
T
rcd
TDL+TRP+2
TRP+TWR+1
Row Row Row
Row
Col
Row
Col
Row
Col