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22 SA-1110 Developer’s Manual
Introduction
Table 1-1. Features of the SA-1110 CPU
• High Performance
— 150 Dhrystone 2.1 MIPS @ 133 MHz
— 235 Dhrystone 2.1 MIPS @ 206 MHz
• Low power (normal mode)†
— <240 mW @1.55 V/133 MHz
— <400 mW @ 1.75 V/206 MHz
• Integrated clock generation
— Internal phase-locked loop (PLL)
— 3.686 MHz oscillator
— 32.768 kHz oscillator
• Power-management features
— Normal (full-on) mode
— Idle (power-down) mode
— Sleep (power-down) mode
• Big and little endian operating modes
• 3.3 V I/O interface
• 256-pin mini-BGA package (mBGA)
• 32-way set-associative caches
— 16 Kbyte instruction cache
— 8 Kbyte write-back data cache
• 32-entry memory-management units
— Maps 4 Kbyte, 8 Kbyte, or 1 Mbyte
• Write buffer
— 8-entry, between 1 and 16 bytes each
• Read buffer
— 4-entry,1,4,or8words
• Memory bus
— Interfaces to ROM, synchronous
mask ROM (SMROM), Flash,
SRAM, SRAM-like variable latency
I/O, DRAM, and synchronous DRAM
(SDRAM)
— Supports two PCMCIA sockets
† Power dissipation, particularly in idle mode, is strongly dependent on the details of the system design.
Table 1-2. Changes to the SA-1110 Core from the SA-110
• Data cache reduced from 16 Kbyte to
8 Kbyte
• Interrupt vector address adjust capability
• Read buffer (nonblocking)
• Minicache for alternate data caching
• Hardware breakpoints
• Memory-management unit (MMU)
enhancements
• Process ID mapping