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SA-1110 Developer’s Manual 103
System Control Module
9.5.3.5 The Sleep Wake-Up Sequence
When a valid wake-up event is detected and there is no BATT_FAULT, the SA-1110 begins a
wake-up sequence. If BATT_FAULT is asserted, then the wake-up event is ignored. VDD_FAULT
is always ignored at this time because the VDDI supply is disabled at this time. The wake-up
sequence occurs in three steps.
• In the first step of the wake-up sequence, the following actions occur:
a. The PWR_EN pin is asserted, indicating that the external supply must apply power on the
VDDI pins.
b. An internal timer begins to time the power ramp. This timer waits for approximately
10 ms.
c. The 3.686-MHz oscillator is enabled for operation if it was originally programmed to be
disabled.
d. If BATT_FAULT is asserted at any time during the sleep wake-up sequence, the power
manager transitions back to sleep mode through the fault state.
• In the second step of the wake-up sequence (after the power ramp timer has expired), the
following actions occur:
a. A second internal timer begins to time the 3.686-MHz oscillator as it begins to ramp up to
speed. This timer waits for 150 ms. If the OPDE bit in the PCFR is zero, then the
oscillator was never disabled and this timer is not used. In this case, the power manager
transitions to the third step directly without waiting for the oscillator timer to complete.
b. If BATT_FAULT or VDD_FAULT is asserted at any time during the oscillator ramp, the
power manager transitions back to sleep mode through the fault state.
• In the third step of the wake-up sequence (after the 3.6864-MHz oscillator is stabilized), the
following actions occur:
a. The SA-1110 internal reset is negated and the CPU begins a normal boot sequence.
b. The RESET_OUT pin is negated, indicating that the SA-1110 is about to perform a fetch
from the reset vector location.
During the fault state entered through the assertion of VDD_FAULT or BATT_FAULT, the
following actions occur:
• All potential wake-up sources are cleared (all GPIO edge detects and the RTC alarm interrupt).
• The power manager wake-up source register (PWER) is loaded with 0x0000 0003 and bits 0
and1oftheGFERandtheGRER(seetheSection 9.1, “General-Purpose I/O” on page 9-73)
are set. This limits the potential wake-up sources to a rising or falling edge on GP 0 or GP 1.
This wake-up fault state is provided to prevent spurious events from causing an unwanted
wake-up during a low battery or shorted power supply situation. This fault state setting of
PWSR, GRER, and GFER registers is also the default state of the registers after a hardware
reset.
9.5.3.6 Booting After Sleep Mode
When the SA-1110 boots after sleep mode (or at any other time), it must examine the reset
controller status register (RCSR) to determine why it just booted. This register has bits to indicate
sleep reset, software reset, watchdog reset, or hardware reset (assertion of nRESET). See
Section 9.6, “Reset Controller” on page 9-115 for more details on reset.